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1/13 september 2001 n low power dissipation: i cc =4 m a(max.) at t a =25c n compatible with ttl outputs : v ih = 2v (min.) v il = 0.8v (max) n high current open drain output up to 80 ma description the m74hct7259 is an high speed cmos 8 bit addressable latch/decoder fabricated with silicon gate c 2 mos technology. this device has single data input (d) 8 latch inverted outputs (q0 - q7 ), 3 address inputs (a, b and c), common enable input (enable ) and a common clear input. to operate this device as an addressable latch, data is held on the d input, and the address of the latch into which the data is to be entered is held on the a, b and c inputs. when enable is taken low the data flows through to the address output. the data is stored on the positive going edge of the enable pulse. all unaddressed latches will remain unaffected. with enable in the high state the device is deselected and all latches remain in their previous state, unaffected by changes on the data or address inputs. to eliminate the possibility of entering erroneous data into the latches, the enable should be held high (inactive) while the address lines are changing. if enable is held high and clear is taken low all eight latches are cleared to the high (off) state. if enable is low all latches except the addressed latch will be cleared. the address latch will instead be the complement of the d input, effectively implementing a 3 to 8 line decoder. internal clamp diodes protect the open drain outputs against over voltages due to inductive loads. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hct7259 8 bit addressable latch/decoder/relais driver open drain, inverting output pin connection and iec logic symbols order codes pack. tube t & r dip M74HCT7259B1R sop m74hct7259m1r m74hct7259rm13tr tssop m74hct7259ttr tssop dip sop
m74hct7259 2/13 input and output equivalent circuit pin description truth table d : the level at the data input qi0 : the level before the indicated steady state input conditions were established, (i = 0, 1,...., 7) pin no symbol name and function 1, 2, 3 a, b, c latch select 4, 5, 6, 7, 9, 10, 11, 12 q0 to q7 latch outputs 13 data in data inputs 14 enable latch enable input 15 clear conditional reset input 8 gnd ground (0v) 16 vcc positive supply voltage inputs outputs of addressed latch each other output function clear enable hl d qi0 addressable latch h h qi0 qi0 memory ll d h 8-line demultiplexer l h h h clear all bits to "h" select inputs latch addressed cb a ll l q0 ll hq1 lh l q2 lh h q3 hl l q4 hl h q5 hh l q6 hh h q7
m74hct7259 3/13 logic diagram this logic diagram has not be used to estimate propagation delays
m74hct7259 4/13 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c recommended operating conditions dc specifications symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 100 ma i gnd dc ground current - 800 ma i cc v cc current 50 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 4.5 to 5.5 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time (v cc = 4.5 to 5.5v) 0 to 500 ns symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 4.5 to 5.5 2.0 2.0 2.0 v v il low level input voltage 4.5 to 5.5 0.8 0.8 0.8 v v ol low level output voltage 4.5 i o =20 m a 0.0 0.1 0.1 0.1 v i o =36 ma 0.17 0.26 0.33 0.40 i o =80 ma 0.32 0.40 0.50 0.55 i oz output leakage current 5.5 v i = v ih or v il v out =v cc or gnd 0.1 1 1 m a i i input leakage current 5.5 v i = v cc or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i = v cc or gnd 44080 m a each input in turn : v in = 0.5v or 2.4v all other inputs : v cc or gnd 3.0 3.9 4.0 ma
m74hct7259 5/13 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc symbol parameter test condition value unit v cc (v) c l (pf) r l (k w) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh output transition time 4.5 50 1 3 6 9 14 ns t plz t pzl propagation delay time (data - q ) 4.5 50 1 20 31 39 45 ns 150 24 37 46 55 t plz t pzl propagation delay time (a, b, c - q ) 4.5 50 1 25 39 49 59 ns 150 29 45 56 65 t plz t pzl propagation delay time (enable - q ) 4.5 50 1 21 33 41 50 ns 150 25 39 49 59 t plz t pzl propagation delay time (clear - q ) 4.5 50 1 19 30 38 44 ns 150 23 36 45 54 t w(l) minimum pulse width (clear ) 4.5 50 1 7 15 19 25 ns t w(l) minimum pulse width (enable ) 4.5 50 1 7 15 19 25 ns t s minimum set-up time 4.5 50 1 4 10 13 19 ns t h minimum hold time 4.5 50 1 5 5 5 ns symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c pd power dissipation capacitance (note 1) 96 pf
m74hct7259 6/13 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r t = z out of pulse generator (typically 50 w ) waveform 1 : propagation delay time (f=1mhz; 50% duty cycle)
m74hct7259 7/13 waveform 2 : propagation delay time (f=1mhz; 50% duty cycle) waveform 3 : minimum pulse width, setup and hold time (f=1mhz; 50% duty cycle)
m74hct7259 8/13 waveform 4 : minimum pulse width, propagation delay time (f=1mhz; 50% duty cycle) waveform 5 : minimum setup and hold time (f=1mhz; 50% duty cycle)
m74hct7259 9/13 input waveforms (f=1mhz; 50% duty cycle)
m74hct7259 10/13 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
m74hct7259 11/13 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
m74hct7259 12/13 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
m74hct7259 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 13/13

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